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a
FEATURES 500 MHz Driver Operation Driver Inhibit Function 100 ps Edge Matching Guaranteed Industry Specifications 50 Output Impedance >1.5 V/ns Slew Rate Variable Output Voltages for ECL, TTL and CMOS High Speed Differential Inputs for Maximum Flexibility Ultrasmall 20-Lead SOP Package with Built-In Heat Sink APPLICATIONS Automatic Test Equipment Semiconductor Test Systems Board Test Systems Instrumentation and Characterization Equipment
Ultrahigh Speed Pin Driver with Inhibit Mode AD53040
FUNCTIONAL BLOCK DIAGRAM
VCC VCC VEE VEE 39nF VH DATA DATA INH INH VL DRIVER 50 VOUT VLDCPL TVCC VHDCPL 39nF
AD53040
1.0 A/K
THERM
GND
GND
GND
GND
GND
PRODUCT DESCRIPTION
The AD53040 is a complete high speed pin driver designed for use in digital or mixed-signal test systems. Combining a high speed monolithic process with a unique surface mount package, this product attains superb electrical performance while preserving optimum packaging densities and long-term reliability in an ultrasmall 20-lead, SOP package with built-in heat sink. Featuring unity gain programmable output levels of -3 V to +8 V, with output swing capability of less than 100 mV to 9 V, the AD53040 is designed to stimulate ECL, TTL and CMOS logic families. The 500 MHz data rate capacity and matched output impedance allows for real-time stimulation of these digital logic families. To test I/O devices, the pin driver can be switched into a high impedance state (Inhibit Mode), electrically removing the driver from the path. The pin driver leakage current inhibit is typically 100 nA and output charge transfer entering inhibit is typically less than 20 pC.
The AD53040 transition from HI/LO or to inhibit is controlled through the data and inhibit inputs. The input circuitry uses high speed differential inputs with a common-mode range of 3 V. This allows for direct interface to precision differential ECL timing or the simplicity of stimulating the pin driver from a single ended TTL or CMOS logic source. The analog logic HI/LO inputs are equally easy to interface. Typically requiring 10 A of bias current, the AD53040 can be directly coupled to the output of a digital-to-analog converter. The AD53040 is available in a 20-lead, SOP package with a built-in heat sink and is specified to operate over the ambient commercial temperature range of -25C to +85C.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
(All specifications are at TJ = +85 C 5 C, +VS = +12 V 3%, -VS = -7 V 3% unless otherwise noted. All temperature coefficients are measured at TJ = +75 C-95 C). (A 39 nF capacitor must be connected between VCC and VHDCPL and between VEE and VLDCPL.)
Parameter DIFFERENTIAL INPUT CHARACTERISTICS Input Swing (Data to DATA, INH to INH) Max (DATA, DATA) to Min (INH, INH) Max (INH, INH) to Min (Data, DATA) Bias Current REFERENCE INPUTS Bias Currents OUTPUT CHARACTERISTICS Logic High Range -50 -2 Min Typ ECL 10 +50 +8 Max 2 2 Units Volts Volts A A Volts Test Conditions
AD53040-SPECIFICATIONS
VIN = -2 V, 0.0 V VL , V H = 5 V DATA = H, VH = -2 V to +8 V VL = -3 V (VH = -2 V to +6 V) VL = -1 V (VH = +6 V to +8 V) DATA = L, VL = -3 V to +5 V, VH = +6 V VL = -0.05 V, VH = +0.05 V and VL = -2 V, VH = +7 V DATA = H, VH = -2 V to +8 V, VL = -3 V DATA = H, VH = -2 V to +8 V, VL = -3 V DATA = L, VL = -3 V to +5 V, VH = +6 V DATA = L, VL = -3 V to +5 V, VH = +6 V VL, VH = 0 V, +5 V and -3 V, 0 V DATA = H, VH = +3 V, VL = 0 V, IOUT = 30 mA VOUT = -3 V to +8 V CBYP = 39 nF, VH = +7 V, VL = -2 V Output to -3 V, VH = +8 V, VL = -1 V, DATA = H and Output to +8 V, VH = +6 V, VL = -3 V, DATA = L VS = VS 3%
Logic Low Range Amplitude (VH and VL) Absolute Accuracy VH Offset VH Gain + Linearity Error VL Offset VL Gain + Linearity Error Offset TC, VH or VL Output Resistance Output Leakage Dynamic Current Limit Static Current Limit
-3 0.1
+5 9
Volts Volts
-100 0.3 5 -100 0.3 5 0.5 47
45 -1.0
+100 mV % of VH + mV +100 mV % of VL + mV mV/C 49 +1.0 A mA mA
150 65
PSRR, Drive Mode DYNAMIC PERFORMANCE, DRIVE (VH and VL ) Propagation Delay Time Propagation Delay TC Delay Matching, Edge to Edge Rise and Fall Time 1 V Swing 3 V Swing 5 V Swing Rise and Fall Time TC 1 V Swing 3 V Swing 5 V Swing Overshoot, Undershoot and Preshoot
35
dB
1.5 2 100
ns ps/C ps
Measured at 50%, VH = +400 mV, VL = -400 mV Measured at 50%, VH = +400 mV, VL = -400 mV Measured at 50%, VH = +400 mV, VL = -400 mV Measured 20%-80%, VL = 0 V, VH = 1 V Measured 10%-90%, VL = 0 V, VH = 3 V Measured 10%-90%, VL = 0 V, VH = 5 V Measured 20%-80%, VL = 0 V, VH = 1 V Measured 10%-90%, VL = 0 V, VH = 3 V Measured 10%-90%, VL = 0 V, VH = 5 V a. VL , VH = 0.0 V, 1.0 V b. VL, VH = 0.0 V, 3.0 V c. VL, VH = 0.0 V, 5.0 V VL = 0 V, VH = 0.5 V VL = 0 V, VH = 0.5 V VL = 0 V, VH = 2 V, Pulsewidth = 2.5 ns/7.5 ns, 30 ns/100 ns
0.8 1.7 2.4 1 2 3 (1% +50 mV)
ns ns ns ps/C ps/C ps/C % of Step + mV
Settling Time to 15 mV to 4 mV Delay Change vs. Pulsewidth
40 8 50
ns s ps
-2-
REV. B
AD53040
Parameter DYNAMIC PERFORMANCE, DRIVE (VH and VL ) (Continued) Minimum Pulsewidth 3 V Swing 5 V Swing Toggle Rate DYNAMIC PERFORMANCE, INHIBIT Delay Time, Active to Inhibit Delay Time, Inhibit to Active I/O Spike Output Capacitance POWER SUPPLIES Total Supply Range Positive Supply Negative Supply Positive Supply Current Negative Supply Current Total Power Dissipation Temperature Sensor Gain Factor Min Typ Max Units Test Conditions
1.7 2.6 500
ns ns MHz
4.0 ns Input, 10%/90% Output, VL = 0 V, VH = 3 V 6.0 ns Input, 10%/90% Output, VL = 0 V, VH = 5 V VL = -1.8 V, VH = -0.8 V, VOUT > 600 mV p-p Measured at 50%, VH = +2 V, VL = -2 V Measured at 50%, VH = +2 V, VL = -2 V VH = 0 V, VL = 0 V Driver Inhibited
2 2 <200 5 19 +12 -7
5 5
ns ns mV, p-p pF V V V mA mA W A/K
1.15 1.0
75 75 1.43
RLOAD = 10 K, VSOURCE = +12 V
NOTES Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
Power Supply Voltage +VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V -VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8 V +VS to -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 V Inputs DATA, DATA, INH, INH . . . . . . . . . . . . . . . . +5 V, -3 V DATA to DATA, INH to INH . . . . . . . . . . . . . . . . . . 3 V VH, VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . +9 V, -4 V VH to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V, 0 V Outputs VOUT Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite2 VOUT Range in Inhibit Mode VHDCPL . . . . . Do Not Connect Except for Capacitor to VCC VLDCPL . . . . . Do Not Connect Except for Capacitor to VEE THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V, 0 V Environmental Operating Temperature (Junction) . . . . . . . . . . . . . . +175C Storage Temperature . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec)3 . . . . . . . . . . +260C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute maximum limits apply individually, not in combination. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Output short circuit protection is guaranteed as long as proper heat sinking is employed to ensure compliance with the operating temperature limits. 3 To ensure lead coplanarity ( 0.002 inches) and solderability, handling with bare hands should be avoided and the device should be stored in environments at 24 C 5C (75F 10F) with relative humidity not to exceed 65%.
ORDERING GUIDE
Shipment Method, Quantity Per Package Shipping Container Option RP-20
Model
Package Description
AD53040KRP 20-Lead Power SOIC Tube, 38 Pieces
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD53040 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-3-
AD53040
PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION
VCC 1 VCC 2 VHDCPL 3 GND 4 VOUT 5 GND 6 VLDCPL 7 VEE VEE 8 9
Pin Name VCC
Pin Number 1, 2
Pin Functional Description Positive Power Supply. Both pins should be connected to minimize inductance and allow maximum speed of operation. VCC should be decoupled to GND with a low inductance 0.1 F capacitor. Negative Power Supply. Both pins should be connected to keep the inductance down and allow maximum speed of operation. VEE should be decoupled to GND with a low inductance 0.1 F capacitor. Device Ground. These pins should be connected to the circuit board's ground plane at the pins. Analog Input that sets the voltage level of a Logic 0 of the driver. Determines the driver output for DATA > DATA. Analog input that sets the voltage level of a Logic 1 of the driver. Determines the driver output for DATA > DATA. The Driver Output. The nominal output impedance is 50 . Internal supply decoupling for the output stage. This pin is connected to VCC through a 39 nF minimum capacitors. Internal supply decoupling for the output stage. This pin is connected to VEE through a 39 nF minimum capacitors. ECL compatible input that control the high impedance state of the driver. When INH > INH, the driver goes into a high impedance state. ECL compatible inputs that determines the high and low state of the driver. Driver output is high for DATA > DATA. Temperature Sensor Start-Up Pin. This pin should be connected to VCC. Temperature Sensor Output Pin. A resistor (10K) should be connected between THERM and VCC. The approximate die temperature can be determined by measuring the current through the resistor. The typical scale factor is 1 A/K. DATA 0 1 0 1
20 THERM 19 TVCC 18 VH
AD53040
TOP VIEW (Not to Scale) COPPER SLUG UP
17 GND 16 GND 15 VL 14 GND 13 DATA 12 DATA 11 INH
VEE
8, 9
INH 10
Table I. Pin Driver Truth Table
GND
4, 6, 14, 16, 17
DATA 1 0 1 0
INH 0 0 1 1
INH 1 1 0 0
Output State VL VH Hi-Z Hi-Z
VL
15
VH
18
Table II. Package Thermal Characteristics
VOUT VHDCPL
5 3
Air Flow, FM 0 50 400 4 4 4
JC,
C/W
JA,
C/W
50 49 34
VLDCPL
7
INH, INH 10, 11
DATA, DATA
13, 12
TVCC THERM
19 20
-4-
REV. B
AD53040
APPLICATION INFORMATION Power Supply Distribution, Bypassing and Sequencing
The AD53040 draws substantial transient currents from its power supplies when switching between states and careful design of the power distribution and bypassing is key to obtaining specified performance. Supplies should be distributed using broad, low inductance traces or (preferably) planes in a multilayered board with a dedicated ground-plane layer. All of the device's power supply pins should be used to minimize the internal inductance presented by the part's bond wires. Each supply must be bypassed to ground with at least one 0.1 F capacitor; chipstyle capacitors are preferable as they minimize inductance. One or more 10 F (or greater) Tantalum capacitors per board are also advisable to provide additional local energy storage. The AD53040's current-limit circuitry also requires external bypass capacitors. Figure 1 shows a simplified schematic of the positive current-limit circuit. Excessive collector current in output transistor Q49 creates a voltage drop across the 10 resistor, which turns on PNP transistor Q48. Q48 diverts the risingedge slew current, shutting down the current mirror and removing the output stage's base drive. The VHDCPL pin should be bypassed to the positive supply with a 0.039 F capacitor, while the VLDCPL pin (not shown) requires a similar capacitor to the negative supply- these capacitors ensure that the AD53040 doesn't current limit during normal output transitions up the its full 9 V rated step size. Both capacitors must have minimumlength connections to the AD53040. Here again, chip capacitors are ideal.
VPOS 10 Q48 10% VHDCPL
Several points about the current-limit circuitry should be noted. First, the limiting currents are not tightly controlled, as they are functions of both absolute transistor VBES and junction temperature; higher dc output current is available at lower junction temperatures. Second, it is essential to connect the VHDCPL capacitor to the positive supply (and the VLDCPL capacitor to the negative supply)--failure to do so causes considerable thermal stress in the current-limiting resistor(s) during normal supply sequencing and may ultimately cause them to fail, rendering the part nonfunctional. Finally, the AD53040 may appear to function normally for small output steps (less than 3 V or so) if one or both of these capacitors is absent, but it will exhibit excessive rise or fall times for steps of larger amplitude. The AD53040 does not require special power-supply sequencing. However, good design practice dictates that digital and analog control signals not be applied to the part before the supplies are stable. Violating this guideline will not normally destroy the part, but the active inputs can draw considerable current until the main supplies are applied.
Digital Input Range Restrictions
Total range amongst all digital signals (DATA, DATA, INH, and INH) has to be less than or equal to 2 V to meet specified timing. The device will function above 2 V with reduced performance up to the absolute maximum limit. This performance degradation might not be noticed in all modes of operation. Of all the six possible transitions (VH v VL, VL v VH, VH v INH, INH v VH, VL v INH and INH v VL), there may be only one that would show a degradation, usually in delay time. Taken to the extreme, the driver may fail to achieve a proper output voltage, output impedance or may fail to fully inhibit. An example of a scenario that would not work for the AD53040 is if the part is driven using 5 V single-ended CMOS. One pin of each differential input would be tied to a +2.5 V reference level and the logic voltages would be applied to the other. This would meet the Absolute Maximum Rating of 3 V because the max differential is 2.5 V. It is however possible, for example for 0.0 V to be applied to the INH input and +5 V to be applied to the DATA input. This 5 V difference far exceeds the 2.0 V limitation given above. Even using 3 V CMOS or TTL the difference between logic high and logic low is greater than or equal to 3 V which will not properly work. The only solution is to use resistive dividers or equivalent to reduce the voltage levels.
RISING-EDGE SLEW CONTROL CURRENT LEVEL-SHIFTED LOGIC DRIVE
VH VNEG Q49
OUT
5.12V
Q50
550mV /DIV
Figure 1. Simplified Schematic of the AD53040 Output Stage and Positive Current Limit Circuitry
-380mV 66.25ns
500ps/DIV
71.25ns
Figure 2. 5 V Output Swing
REV. B
-5-
AD53040
NOTE: 1. 50 TERMINATION TO BE AS CLOSE TO RECEIVER AS POSSIBLE. (END OF TRACE MARKED BY *). THROUGH SMA CONNECTS BETWEEN MC10EL16 OUTPUTS AND DUT. 2. NO VIAS ALLOWED ON VOUT LINE. 3. SMA ON VOUT TO BE MOUNTED ON ITS SIDE FOR BEST IMPEDANCE MATCH. 4. ONE DIMENSION OF BOARD TO BE 4-1/2 INCHES. 5. DUT PACKAGE IS TO BE CENTERED ON BOARD. 6. ALL RESISTORS AND NONELECTROLYTIC CAPS ARE 0805-SIZE SURFACE MOUNT. 7. SEE DATA SHEET FOR HIDDEN POWER AND GROUND PINS ON LOGIC GATES. 8. ALL 100nF BYPASS CAPACITORS TO BE LOCATED CLOSE TO PACKAGE. 9. PCB IS TO BE 4-LAYER WITH POWER GND ( ) AND -2V AS INNER PLANES. C2 0.1 F +VS
VLOW VHIGH 50 DATA J1 SMB U1 MC10EL16 7 6 5 -5.2V C21 0.1 F -2V C14 0.1 F INH J2 SMB U2 MC10EL16 8 7 6 5 -5.2V C13 0.01 F C22 0.1 F -2V C15 0.1 F R1 50 R2 50 J6 SMB JP1 1 TP GND JP2 1 TP JP3 P1 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 DB15 1 TP -VS +VS 50 SMB J5 R4 50 R3 50 J3 SMB 50 SMB J4 C1 0.1 F
50 R6 50
2 3
18
C19 0.1 F
J8 SIDESMB C18 5pF TEST_LD
C12 0.01 F
THERM TVCC TH 50 VH VL
R7 50 HQG1 +VS IL+ G2H U3 VOUT 50 C16 0.039 F
J7 SIDESMB VOUT
1 50 R5 50 2 3
AD53040
DATA IL- INH -VS C17 0.039 F PWR GND G2L
C3 0.1 F
VLOW -2V VHIGH -VS THERM -5.2V +VS
-VS VEE -5.2V VCC C9 0.1 F C10 0.1 F C11 0.1 F GND
+
C4 1F
C7 1F
C6 1F
C5 1F
C8 0.1 F
Figure 3. Evaluation Board Schematic
-6-
REV. B
AD53040
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Thermally Enhanced Small Outline Package (PSOP) (RP-20)
0.5118 (13.00) 0.4961 (12.60)
20 11
0.2992 (7.60) 0.2914 (7.40)
1
HEAT SINK
10
0.1890 (4.80) 0.4193 (10.65) 0.1791 (4.55) 0.3937 (10.00)
PIN 1 0.3340 (8.61) 0.3287 (8.35) 0.1043 (2.65) 0.0926 (2.35) 8 0 0.0118 (0.30) 0.0500 (1.27) 0.0040 (0.10) BSC STANDOFF 0.0201 (0.51) SEATING 0.0500 (1.27) 0.0130 (0.33) PLANE 0.0057 (0.40) 0.0295 (0.75) x 45 0.0098 (0.25)
REV. B
-7-
PRINTED IN U.S.A.
C3003b-0-11/99

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